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Yiorgos Makris

Yiorgos Makris

Professor - Electrical Engineering

Professional Preparation

PhD - Computer Engineering
University of California San Diego - 2001
MS - Computer Engineering
University of California, San Diego - 1998
Diploma - Computer Engineering and Informatics
University of Patras, Greece - 1995

Research Areas

Awards and Honors
  • IEEE Computer Society, Meritorious Service Award, Apr ’10
  • National Academy of Engineering (NAE) Frontiers of Engineering Symposium Participant, Sep ’07
  • IEEE Computer Society, Certificate of Appreciation, Oct ’06, Oct ’08
  • Sheffield Distinguished Teaching Award, Faculty of Engineering, May ’06 
  • Yale University, Junior Faculty Fellowship, Jan ’05 - Dec ’05 
  • Paul Moore Award for Developing Course “Semiconductors, Computers and Communications”, May ’03 ($10K)
  • Paul Moore Award for Developing Course “Digital Systems Testing And Design for Testability”, May ’01 ($11K)
  • INTEL Corp. Recognition Award, Sep ’96
  • UCSD School of Engineering Industrial Fellowsh


Y. Jin, Y. Makris, Hardware Trojans in Wireless Cryptographic Integrated Circuits, Special issue of IEEE Design & Test of Computers (D&T) on Verifying Physical Trustworthiness of Integrated Circuits and Systems, vol. 27, no. 1, pp. 26-35, 2010 2010 - Publication
H-G. Stratigopoulos, P. Drineas, M. Slamani, Y. Makris, RF Specification Test Compaction using Learning Machines, IEEE Transactions on Very Large Scale Integration (T.VLSI), vol. 18, no. 6, pp. 1002-1006, 2010 2010 - Publication
N. Kupp, P. Drineas, M. Slamani, Y. Makris, On Boosting the Accuracy of Non-RF to RF Correlation-Based Specification Test Compaction, Journal of Electronic Testing Theory and Applications (JETTA), Springer, vol. 25, no. 6, pp. 309-321, 2009 2009 - Publication
S. Almukhaizim, F. Shi, E. Love, Y. Makris, Soft Error Tolerance and Mitigation in Asynchronous Burst Mode Circuits, IEEE Transactions on Very Large Scale Integration (T.VLSI), vol. 17, no. 7, pp. 869-882, 2009 2009 - Publication
F. Shi, Y. Makris, Enhancing Simulation Accuracy through Advanced Hazard Detection in Asynchronous Circuits, IEEE Transactions on Computers (T.COMP), vol. 58, no. 3, pp. 394-408, 2009 2009 - Publication
H-G. D. Stratigopoulos, Y. Makris, Error Moderation in Low-Cost Machine Learning-Based Analog/RF Testing, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (T. CAD), vol. 27, no. 2, pp. 339-351, 2008 2008 - Publication