Sam Shichijo

Ph.D. - Electrical Engineering
University of Illinoise at Urbana-Champaign - 1980

M.S. - Electrical Engineering
University of Illinois at Urbana-Champaign - 1978

B.S.E.E. - Electronic Engineering
University of Tokyo - 1976

Solving the requirement for analog transistors in advanced CMOS SoC technologies K. Benaissa, , H. Shichijo, G. Baldwin, S. Liu, P. Srinivasan, F. Hou, B. Obradovic, S. Yu, H. Yang, S.Venkataraman, H. Lu, submitted to 2009 Symposium on VLSI Technology. 2009 - Publication

“Solving the requirement for analog transistors in advanced CMOS SoC technologies” K. Benaissa, , H. Shichijo, G. Baldwin, S. Liu, P. Srinivasan, F. Hou, B. Obradovic, S. Yu, H. Yang, S.Venkataraman, H. Lu, submitted to 2009 Symposium on VLSI Technology. 2009 - Publication

"45nm Low-Power CMOS SoC Technology with Aggressive Reduction of Random Variation for SRAM and Analog Transistors"  S. Ekbote, K. Benaissa, B. Obradovic, S. Liu, H. Shichijo, F. Hou, T. Blythe, T. W. Houston, S. Martin, R. Taylor, A. Singh, H. Yang, G. Baldwin, Digest of Technical Papers, 2008 Symposium on VLSI Technology, pp.160-161 2008 - Publication

45nm Low-Power CMOS SoC Technology with Aggressive Reduction of Random Variation for SRAM and Analog Transistors S. Ekbote, K. Benaissa, B. Obradovic, S. Liu, H. Shichijo, F. Hou, T. Blythe, T. W. Houston, S. Martin, R. Taylor, A. Singh, H. Yang, G. Baldwin, Digest of Technical Papers, 2008 Symposium on VLSI Technology, pp.160-161. 2008 - Publication

Will Continued Process-Node Shrinks Kill High-Performance Analog Design? Evening Panel Discussion, Savoj, J.; Rich, D.; Forejt, B.; Kinget, P.; Un-Ku Moon; Oprysko, M.; Razavi, B.; Shichijo, H.; Wang, A.; Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, Sept. 2005, pp.616- 617. 2005 - Publication

MIMCAP Dynamic Leakage Impact to Switched-Capacitor Sigma-Delta Converters in Deep-Submicron Digital CMOS Processes, Weibiao Zhang, Yin Hu and Hisashi Shichijo, Proceedings of Technical Papers, 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation & Test, pp.307-310, April 27-29, 2005, Hsinchu, Taiwan. 2005 - Publication

“Device and Technology Evolution for Si-Based RF Integrated Circuits”, H.B. Bennett, R. Brederlow, J. Costa, P.E. Cottrell, M. Huang, A. A. Immorlica, Jr. J.-E. Mueller, M. Racanelli, H. Shichijo, C.E. Weitzel, and B. Zhao, IEEE Transactions on Electron Devices, Volume 52, Issue 7, July 2005 Page(s):1235 - 1258. 2005 - Publication

 "Device Device and Technology Evolution for Si-Based RF Integrated Circuits", H.B. Bennett, R. Brederlow, J. Costa, P.E. Cottrell, M. Huang, A. A. Immorlica, Jr. J.-E. Mueller, M. Racanelli, H. Shichijo, C.E. Weitzel, and B. Zhao, IEEE Transactions on Electron Devices, Volume 52,  Issue 7,  July 2005 Page(s):1235 - 1258. 2005 - Publication

Professional Affiliations

Fellow, Institute of Electrical and Electronics Engineers (IEEE)

Patents Issued

• 7,250,334 "Metal insulator metal (MIM) capacitor fabrication with sidewall spacers and aluminum cap (ALCAP) top electrode"
• 6,764,892 "Device and method of low voltage SCR protection for high voltage failsafe ESD applications"
• 6,753,202 "CMOS photodiode having reduced dark current and improved light sensitivity and responsivity"
• 6,621,064 "CMOS photodiode having reduced dark current and improved light sensitivity and responsivity"
• 6,576,959 "Device and method of low voltage SCR protection for high voltage failsafe ESD applications"
• 6,548,874 "Higher voltage transistors for sub micron CMOS processes"
• 6,512,280 "Integrated CMOS structure for gate-controlled buried photodiode"
• 6,392,263 "Integrated structure for reduced leakage and improved fill-factor in CMOS pixel"
• 6,303,420 "Integrated bipolar junction transistor for mixed signal circuits"
• 5,959,308 "Epitaxial layer on a heterointerface"
• 5,894,145 "Multiple substrate bias random access memory device"
• 5,595,925 "Method for fabricating a multiple well structure for providing multiple substrate bias for DRAM device formed therein"
• 5,290,719 "Method of making complementary heterostructure field effect transistors"
• 5,238,869 "Method of forming an epitaxial layer on a heterointerface"
• 5,214,298 "Complementary heterostructure field effect transistors"
• 5,164,917 "Vertical one-transistor DRAM with enhanced capacitance and process for fabricating"
• 5,065,132 "Programmable resistor and an array of the same"
• 4,914,053 "Heteroepitaxial selective-area growth through insulator windows"
• 4,910,164 "Method of making planarized heterostructures using selective epitaxial growth"
• 4,713,678 "dRAM cell and method"
• 4,545,034 "Contactless tite RAM"