Benjamin Carrion Schaefer

Assistant Professor - Electrical Engineering
+1(972) 883-4531
UTD profile
Tags: FPGA Hihg-Level Synthesis Reconfiguralble Computing EDA Design Automation VLSI design

Professional Preparation

PhD - Electrical Engineering
The University of Birmingham, UK - 2003


Method and Apparatus for Design Space Exploration - Other
Method and Apparatus for Incremental Design Space Exploration - Other
Learning from the Past: Efficient High-level Synthesis Design Space Exploration for FPGAs 2022 - Journal Article
Leveraging Automatic High-Level Synthesis Resource Sharing to Maximize Dynamical Voltage Overscaling with Error Control 2022 - Journal Article
Building Complete Heterogeneous Systems-on-Chip in C: From Hardware Accelerators to CPUs 2021 - Journal Article
Area Efficient Functional Locking through Coarse Grained Runtime Reconfigurable Architectures 2021 - Conference Paper
A Transistor-Level Fabric for Design Obfuscation, 2020 - Conference Paper
Bespoke Approximate Behavioral Processors 2020 - Conference Paper
DECOY: DEflection-Driven HLS-Based Computation Partitioning for Obfuscating Intellectual PropertY 2020 - Conference Paper
Efficient Functional Locking of Behavioral IPs 2020 - Conference Paper