Benjamin Carrion Schaefer

Assistant Professor - Electrical Engineering
+1(972) 883-4531
UTD profile
Tags: FPGA Hihg-Level Synthesis Reconfiguralble Computing EDA Design Automation VLSI design

Professional Preparation

PhD - Electrical Engineering
The University of Birmingham, UK - 2003


Enabling High-Level Synthesis Resource Sharing Design Space Exploration in FPGAs Through Automatic Internal Bitwidth Adjustments 2017 - Journal Article
Probabilistic Multiknob High-Level Synthesis Design Space Exploration Acceleration 2016 - Journal Article
S2CBench: Synthesizable SystemC Benchmark Suite for High-Level Synthesis 2014 - Journal Article
Machine-learning based simulated annealer method for high level synthesis design space exploration 2014 - Conference Paper
Allocation of FPGA DSP-macros in multi-process high-level synthesis systems 2014 - Conference Paper
Acceleration of the Discrete Element Method: From RTL to C-Based Design 2013 - Other
Divide and conquer high-level synthesis design space exploration 2012 - Journal Article
Machine learning predictive modelling high-level synthesis design space exploration 2012 - Journal Article
Precision tunable RTL macro-modelling cycle-accurate power estimation 2011 - Journal Article
Design Space Exploration Acceleration Through Operation Clustering 2010 - Journal Article