Benjamin Carrion Schaefer

+1(972) 883-4531
ECN4.510
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PhD - Electrical Engineering
The University of Birmingham, UK - 2003

Method and Apparatus for Incremental Design Space Exploration - Other

Method and Apparatus for Design Space Exploration - Other

Leveraging Automatic High-Level Synthesis Resource Sharing to Maximize Dynamical Voltage Overscaling with Error Control 2022 - Journal Article

Learning from the Past: Efficient High-level Synthesis Design Space Exploration for FPGAs 2022 - Journal Article

Building Complete Heterogeneous Systems-on-Chip in C: From Hardware Accelerators to CPUs 2021 - Journal Article

Area Efficient Functional Locking through Coarse Grained Runtime Reconfigurable Architectures 2021 - Conference Paper

Flexible Runtime Reconfigurable Computing Overlay Architecture and Optimization for Dataflow Applications 2020 - Conference Paper

Efficient and Robust High-Level Synthesis Design Space Exploration through offline Micro-kernels Pre-characterization, 2020 - Conference Paper

Efficient Functional Locking of Behavioral IPs 2020 - Conference Paper

Hardware-assisted Simulation of Voltage-behind-reactance Models of Electric Machines on FPGA 2020 - Journal Article