Benjamin Carrion Schaefer

Assistant Professor - Electrical Engineering
+1(972) 883-4531
UTD profile
Tags: FPGA Hihg-Level Synthesis Reconfiguralble Computing EDA Design Automation VLSI design

Professional Preparation

PhD - Electrical Engineering
The University of Birmingham, UK - 2003


Method and Apparatus for Design Space Exploration - Other
Method and Apparatus for Incremental Design Space Exploration - Other
Area Efficient Functional Locking through Coarse Grained Runtime Reconfigurable Architectures 2021 - Conference Paper
A Transistor-Level Fabric for Design Obfuscation, 2020 - Conference Paper
Bespoke Approximate Behavioral Processors 2020 - Conference Paper
DECOY: DEflection-Driven HLS-Based Computation Partitioning for Obfuscating Intellectual PropertY 2020 - Conference Paper
Efficient Functional Locking of Behavioral IPs 2020 - Conference Paper
Efficient and Robust High-Level Synthesis Design Space Exploration through offline Micro-kernels Pre-characterization, 2020 - Conference Paper
Flexible Runtime Reconfigurable Computing Overlay Architecture and Optimization for Dataflow Applications 2020 - Conference Paper
Hardware-assisted Simulation of Voltage-behind-reactance Models of Electric Machines on FPGA 2020 - Journal Article