Ph.D. - Computer Engineering
Case Western Reserve University - 1993
M.S. - Electrical Engineering
University of Tehran - 1986
B.S. - Electrical Engineering
University of Tehran - 1984
Teaching and Research Interests
- Digital systems testability, SoC design & test issues, DFT methodologies, test synthesis, test data compression, fault modeling and testing of ultra high-speed SoCs, testing signal integrity in gigahertz interconnects.
- Computer aided design including digital circuit design, optimization, RTL estimation, high-level synthesis and low power design methodologies.
- VLSI system modeling/architecture, hardware description languages, parallel processing, sensor & body-area network architectures, special-purpose microprocessor design and packet processing architecture.
M. Nourani and A. Radhakrishnan, Testing on-Die Process Variation in Nanometer VLSI,'' in IEEE Design & Test of Computers, pp. 438-451, Nov./Dec. 2006. 2006 - Publication
M. Akhbarizadeh and M. Nourani, Throughput Increase in Packet Forwarding Engines Using Adaptive Block-Selection Scheme, in IEEE Communications Letters, pp. 838-840, vol. 9, no. 9, Sept. 2005. 2005 - Publication
B. Bornoosh, R. Dehghani, M. Mehrara, A. Afzali-Kusha, S. M. Atarodi and M. Nourani, Reduced Complexity 1-Bit High-Order Digital Delta-Sigma Modulator for Low-Voltage Fractional-N Frequency Synthesis Applications, in IEEE Proceedings Circuits, Devices & Systems, pp. 471-477, vol. 152, no. 5, Oct. 2005. 2005 - Publication
M. Akhbarizadeh, M. Nourani and C. Cantrell, TCAM Implementation of IP Forwarding Engine Using Prefix Segregation Scheme, in IEEE Micro Magazine, pp. 48-63, July/Aug. 2005. 2005 - Publication
J. Chin and M. Nourani, FITS: An Integrated ILP-Based Test Scheduling Environment, in IEEE Transactions on Computers, vol. 54, no. 12, pp. 1598-1613, Dec. 2005. 2005 - Publication
The University of Texas at Dallas [2004–Present]
The University of Texas at Dallas [1999–2004]
Visiting Assistant Professor
Case Western Reserve University [1998–1999]
University of Tehran [1995–1998]
Testing for Signal Integrity and Process Variations
2004–2004 Texas Instruments Inc., (Dallas, TX), Aug. 4, 2004.
TCAM-Based Parallel Architectures for Packet Processing
2004–2004 Invited Nerd Lunch Presentation, Cisco Systems, Inc., (San Jose, CA), Oct. 13, 2004.
New Challenges in Testing High-Speed System-on-Chips
2005–2005 Department of Computer Science & Engineering, University of North Texas, (Denton, TX), Feb. 16, 2005.
Testing Signal Integrity in Gigahertz SoCs
2007–2007 Department of Electrical & Computer Engineering, University of Texas at Austin, (Austin, TX), Sept. 26, 2003., November 16, 2007.
Ripple-Precharge TCAM for Low-Power Applications
2006–2006 Texas Instruments Inc., (Dallas, TX), Aug. 10, 2006.
Honors and Awards
- Senior Member, IEEE
- Best Paper Award at the IEEE International Conference on Computer Design, 2004.
- Scalable Multi-Search per Cycle TCAM Architectures for High-Speed Routers (Sponsored by Cisco Systems ; 2004-2005).
- Signal Integrity Fault Modeling and Testing in High-Speed SoCs (Sponsored by the National Science Foundation ; 2001-2006).
- Router-on-Chip: A Port-Sliced Architecture for Terabit Packet Routing Processors (Sponsored the Clark Foundation Research Initiation Grant (2002-2003)
- Energy Efficient VLSI Architectures for Communications and Signal Processing (Sponsored by the Texas Telecommunications Consortium ; 2000-2001)
A new behavioral data analysis system under development at UT Dallas focuses on identifying potential Internet threats, but it comes with a nice bonus. Researchers say the basic idea behind the system – detecting worrisome deviations from normal activity and quickly providing an alert so that immediate measures can be taken – could have application in areas far beyond the Web, such as health-care monitoring. “We proposed a novel platform that thoroughly analyzes network traffic behavior to identify potential internet threats,” said Dr. Mehrdad Nourani, an associate professor of electrical engineering in the University’s Erik Jonsson School of Engineering and Computer Science. “But it could have much broader application.”
Dr. Mehrdad Nourani, assistant professor of electrical engineering at The University of Texas at Dallas (UTD), has been granted a Career Award from the National Science Foundation (NSF) for his work with Very Large Scale Integrated (VLSI) circuits, particularly focusing on self-testing methods for high-speed chip interconnects. The award, worth more than $389,000 over the next five years, is part of the NSF’s Faculty Early Career Development program. The Career Award is the NSF’s most prestigious honor for junior faculty members and recognizes and supports the activities of the teachers and scholars who are most likely to become the academic leaders of the 21st century. Recipients are selected on the basis of creative early career development plans that effectively integrate research and education within the context of the mission of their respective institutions. The VLSI chips Nourani researches essentially are microelectronic circuits with millions of tiny transistors. Such sophisticated chips, often referred to as System-on-Chip (SoC), are used in numerous applications - including computers, cars, airplanes and communication and robotic systems - to perform control and data processing functions.