Ph.D. - Computer Engineering
Case Western Reserve University - 1993
Mehrdad Nourani
Professor - Electrical Engineering
Affiliated Programs: Computer Engineering, Telecommunications Engineering
Professional Preparation
M.S. - Electrical Engineering
University of Tehran - 1986
University of Tehran - 1986
B.S. - Electrical Engineering
University of Tehran - 1984
University of Tehran - 1984
Research Areas
Teaching and Research Interests
- Digital systems testability, SoC design & test issues, DFT methodologies, test synthesis, test data compression, fault modeling and testing of ultra high-speed SoCs, testing signal integrity in gigahertz interconnects.
- Computer aided design including digital circuit design, optimization, RTL estimation, high-level synthesis and low power design methodologies.
- VLSI system modeling/architecture, hardware description languages, parallel processing, sensor & body-area network architectures, special-purpose microprocessor design and packet processing architecture.
Publications
M. Nourani, M. Tehranipoor and N. Ahmed, Low-Transition Test Pattern Generation for BIST-Based Applications,'' in IEEE Transactions on Computers, vol. 57, no. 3, pp. 303-315, March 2008. 2008 - Publication
A. Amirabadi, Y. Mortazavi, A. Afzali-Kusha and M. Nourani, Clock Delayed Domino Logic with Efficient Variable Threshold Voltage Keeper,'' in IEEE Transactions on VLSI, vol. 15, no. 2, pp. 125-134, Feb. 2007. 2007 - Publication
M. Akhbarizadeh, M. Nourani, R. Panigrahy and S. Sharma, A TCAM-Based Parallel Architecture for High-Speed Packet Forwarding,'' in IEEE Transactions on Computers, vol. 56, no. 1, pp. 58-72, Jan. 2007. 2007 - Publication
A. Namazi and M. Nourani, ``Distributed Voting for Fault-Tolerant Nanoscale Systems,'' in Proceedings of International Conference on Computer Design (ICCD), (Lake Tahoe, CA), pp. 568-573, Oct. 2007. 2007 - Publication
A. Broumandnia, J. Shanbehzadeh and M. Nourani, ``Segmentation of Printed Farsi/Arabic Words,'' in Proceedings of IEEE/ACS International Conference on Computer Systems and Applications (AICCSA'07), pp. 761-766, May 2007. 2007 - Publication
A. Broumandnia, J. Shanbehzadeh and M. Nourani, ``Handwritten Farsi/Arabic Word Recognition,'' in Proceedings of IEEE/ACS International Conference on Computer Systems and Applications (AICCSA'07), pp. 767-771, May 2007. 2007 - Publication
M. Faezipour, M. Nourani and R. Panigrahy, ``A Real-Time Worm Outbreak Detection System Using Shared Counters,'' in Proceedings of the IEEE Symposium on High Performance Interconnects (HOTI), (Palo Alto, CA), pp. 65-72, Aug. 2007. 2007 - Publication
M. Nourani and P. Katta, ``Bloom Filter Accelerator for String Matching,'' in Proceedings of the IEEE International Conference on Computer Communications and Networks (ICCCN) (Honolulu, HI), pp. MP2.13-MP2.18, Aug. 2007. 2007 - Publication
Appointments
Associate Professor
The University of Texas at Dallas [2004–Present]
The University of Texas at Dallas [2004–Present]
Assistant Professor
The University of Texas at Dallas [1999–2004]
The University of Texas at Dallas [1999–2004]
Visiting Assistant Professor
Case Western Reserve University [1998–1999]
Case Western Reserve University [1998–1999]
Assistant Professor
University of Tehran [1995–1998]
University of Tehran [1995–1998]
Projects
Ripple-Precharge TCAM for Low-Power Applications
2006–2006 Texas Instruments Inc., (Dallas, TX), Aug. 10, 2006.New Challenges in Testing High-Speed System-on-Chips
2005–2005 Department of Computer Science & Engineering, University of North Texas, (Denton, TX), Feb. 16, 2005.TCAM-Based Parallel Architectures for Packet Processing
2004–2004 Invited Nerd Lunch Presentation, Cisco Systems, Inc., (San Jose, CA), Oct. 13, 2004.Testing for Signal Integrity and Process Variations
2004–2004 Texas Instruments Inc., (Dallas, TX), Aug. 4, 2004.Testing Signal Integrity in Gigahertz SoCs
2007–2007 Department of Electrical & Computer Engineering, University of Texas at Austin, (Austin, TX), Sept. 26, 2003., November 16, 2007.Additional Information
Honors and Awards
- Senior Member, IEEE
- Best Paper Award at the IEEE International Conference on Computer Design, 2004.
Projects
- Scalable Multi-Search per Cycle TCAM Architectures for High-Speed Routers (Sponsored by Cisco Systems ; 2004-2005).
- Signal Integrity Fault Modeling and Testing in High-Speed SoCs (Sponsored by the National Science Foundation ; 2001-2006).
- Router-on-Chip: A Port-Sliced Architecture for Terabit Packet Routing Processors (Sponsored the Clark Foundation Research Initiation Grant (2002-2003)
- Energy Efficient VLSI Architectures for Communications and Signal Processing (Sponsored by the Texas Telecommunications Consortium ; 2000-2001)