Mehrdad Nourani

Professor - Electrical Engineering
Affiliated Programs: Computer Engineering, Telecommunications Engineering
nourani@utdallas.edu
972-883-4391
ECN4924
Faculty Homepage
Tags: Electrical Engineering Computer Engineering

Professional Preparation

Ph.D. - Computer Engineering
Case Western Reserve University - 1993
M.S. - Electrical Engineering
University of Tehran - 1986
B.S. - Electrical Engineering
University of Tehran - 1984

Research Areas

Teaching and Research Interests
  • Digital systems testability, SoC design & test issues, DFT methodologies, test synthesis, test data compression, fault modeling and testing of ultra high-speed SoCs, testing signal integrity in gigahertz interconnects.
  • Computer aided design including digital circuit design, optimization, RTL estimation, high-level synthesis and low power design methodologies.
  • VLSI system modeling/architecture, hardware description languages, parallel processing, sensor & body-area network architectures, special-purpose microprocessor design and packet processing architecture.

Publications

M. Nourani, M. Tehranipoor and N. Ahmed, Low-Transition Test Pattern Generation for BIST-Based Applications,'' in IEEE Transactions on Computers, vol. 57, no. 3, pp. 303-315, March 2008. 2008 - Publication
M. Nourani and P. Katta, ``Bloom Filter Accelerator for String Matching,'' in Proceedings of the IEEE International Conference on Computer Communications and Networks (ICCCN) (Honolulu, HI), pp. MP2.13-MP2.18, Aug. 2007. 2007 - Publication
A. Broumandnia, J. Shanbehzadeh and M. Nourani, ``Handwritten Farsi/Arabic Word Recognition,'' in Proceedings of IEEE/ACS International Conference on Computer Systems and Applications (AICCSA'07), pp. 767-771, May 2007. 2007 - Publication
A. Namazi and M. Nourani, ``Distributed Voting for Fault-Tolerant Nanoscale Systems,'' in Proceedings of International Conference on Computer Design (ICCD), (Lake Tahoe, CA), pp. 568-573, Oct. 2007. 2007 - Publication
M. Akhbarizadeh, M. Nourani, R. Panigrahy and S. Sharma, A TCAM-Based Parallel Architecture for High-Speed Packet Forwarding,'' in IEEE Transactions on Computers, vol. 56, no. 1, pp. 58-72, Jan. 2007. 2007 - Publication
A. Amirabadi, Y. Mortazavi, A. Afzali-Kusha and M. Nourani, Clock Delayed Domino Logic with Efficient Variable Threshold Voltage Keeper,'' in IEEE Transactions on VLSI, vol. 15, no. 2, pp. 125-134, Feb. 2007. 2007 - Publication
M. Faezipour, M. Nourani and R. Panigrahy, ``A Real-Time Worm Outbreak Detection System Using Shared Counters,'' in Proceedings of the IEEE Symposium on High Performance Interconnects (HOTI), (Palo Alto, CA), pp. 65-72, Aug. 2007. 2007 - Publication
A. Broumandnia, J. Shanbehzadeh and M. Nourani, ``Segmentation of Printed Farsi/Arabic Words,'' in Proceedings of IEEE/ACS International Conference on Computer Systems and Applications (AICCSA'07), pp. 761-766, May 2007. 2007 - Publication
M. Akhbarizadeh, M. Nourani, D. Vijayasarathi and P. Balsara, A Non-Redundant Ternary CAM Circuit for Network Search-Engines, in IEEE Transactions on VLSI, vol. 14, no. 3, pp. 268-278, March 2006. 2006 - Publication
K. Shojaee, M. Gholipour, A. Afzali-Kusha and M. Nourani, Comparative Study of Performance and Power Consumption of Asynchronous Pipeline Design Methods,'' in IEICE Electronics Express (ELEX), vol. 3, no. 8, pp. 163-171, April 2006. 2006 - Publication

Appointments

Associate Professor
The University of Texas at Dallas [2004–Present]
Assistant Professor
The University of Texas at Dallas [1999–2004]
Visiting Assistant Professor
Case Western Reserve University [1998–1999]
Assistant Professor
University of Tehran [1995–1998]

Projects

Testing for Signal Integrity and Process Variations
2004–2004 Texas Instruments Inc., (Dallas, TX), Aug. 4, 2004.
TCAM-Based Parallel Architectures for Packet Processing
2004–2004 Invited Nerd Lunch Presentation, Cisco Systems, Inc., (San Jose, CA), Oct. 13, 2004.
New Challenges in Testing High-Speed System-on-Chips
2005–2005 Department of Computer Science & Engineering, University of North Texas, (Denton, TX), Feb. 16, 2005.
Testing Signal Integrity in Gigahertz SoCs
2007–2007 Department of Electrical & Computer Engineering, University of Texas at Austin, (Austin, TX), Sept. 26, 2003., November 16, 2007.
Ripple-Precharge TCAM for Low-Power Applications
2006–2006 Texas Instruments Inc., (Dallas, TX), Aug. 10, 2006.

Additional Information

Honors and Awards
  • Senior Member, IEEE
  • Best Paper Award at the IEEE International Conference on Computer Design, 2004.
Projects
  • Scalable Multi-Search per Cycle TCAM Architectures for High-Speed Routers (Sponsored by Cisco Systems ; 2004-2005).
  • Signal Integrity Fault Modeling and Testing in High-Speed SoCs (Sponsored by the National Science Foundation ; 2001-2006).
  • Router-on-Chip: A Port-Sliced Architecture for Terabit Packet Routing Processors (Sponsored the Clark Foundation Research Initiation Grant (2002-2003)
  • Energy Efficient VLSI Architectures for Communications and Signal Processing (Sponsored by the Texas Telecommunications Consortium ; 2000-2001)    

News Articles

New Data Analysis System Could Do Double Duty
A new behavioral data analysis system under development at UT Dallas focuses on identifying potential Internet threats, but it comes with a nice bonus. Researchers say the basic idea behind the system – detecting worrisome deviations from normal activity and quickly providing an alert so that immediate measures can be taken – could have application in areas far beyond the Web, such as health-care monitoring. “We proposed a novel platform that thoroughly analyzes network traffic behavior to identify potential internet threats,” said Dr. Mehrdad Nourani, an associate professor of electrical engineering in the University’s Erik Jonsson School of Engineering and Computer Science. “But it could have much broader application.”
UTD Electrical Engineering Professor Wins National Science Foundation Career Award
Dr. Mehrdad Nourani, assistant professor of electrical engineering at The University of Texas at Dallas (UTD), has been granted a Career Award from the National Science Foundation (NSF) for his work with Very Large Scale Integrated (VLSI) circuits, particularly focusing on self-testing methods for high-speed chip interconnects. The award, worth more than $389,000 over the next five years, is part of the NSF’s Faculty Early Career Development program. The Career Award is the NSF’s most prestigious honor for junior faculty members and recognizes and supports the activities of the teachers and scholars who are most likely to become the academic leaders of the 21st century. Recipients are selected on the basis of creative early career development plans that effectively integrate research and education within the context of the mission of their respective institutions. The VLSI chips Nourani researches essentially are microelectronic circuits with millions of tiny transistors. Such sophisticated chips, often referred to as System-on-Chip (SoC), are used in numerous applications - including computers, cars, airplanes and communication and robotic systems - to perform control and data processing functions.