Ph.D. - Electrical Engineering
University of California, Berkeley - 1987
Professional Preparation
M.S. - Electrical Engineering
Massachusetts Institute of Technology - 1977
Massachusetts Institute of Technology - 1977
B.E.E. - Electrical Engineering
University of Minnesota - 1975
University of Minnesota - 1975
Research Areas
Research Interests
My research interests center primarily on the design and computer-aided design of integrated circuits. I have ongoing projects in high-speed, energy-efficient DSP block design, low-power (sub-threshold) highdefinition video decoder design, as well as area-efficient and reliable embedded DRAM and SRAM design. Another key research project is cell sizing/selection for global power minimization in digital integrated circuits, including leakage power control, as well as variational sensitivity reduction and yield enhancement. Cell library optimization is also addressed. I am also working on time-to-digital conversion, crystalfree high-precision oscillator design, and all-digital analog-to-digital converter design.Publications
S. Sun and C. Sechen, Post-Layout Comparison of High Performance 64b Static Adders in Energy-Delay Space, Proc. IEEE Int. Conf. on Computer Design (ICCD), Lake Tahoe, CA, October 2007. 2007 - Publication
M. Rahman, H. Tennakoon, and C. Sechen, Optimal Area-versus-Delay Circuit Sizing Using Ex-tended Logical Effort, Proc. Austin Conf. on Integrated Circuits and Systems (ACISC), May 14-15, 2007, Austin, TX. 2007 - Publication
K. H. Chong and C. Sechen, 64b Adder Using Self-Calibrating Differential Output Prediction Logic, submitted February 28, 2007 to: IEEE Journal of Solid-State Circuits. 2007 - Publication
M. Vujkovic, D. Wadkins and C. Sechen, Accurate Post-Layout Power versus Delay Curve Genera-tion, submitted February 26, 2007 to: IEEE Trans. on Computer-Aided Design. 2007 - Publication
Sheng Sun and C. Sechen, Post-Layout Comparison of High Performance 64b Static Adders in En-ergy-Delay Space, submitted February 15, 2007 to: IEEE Transactions on VLSI Systems. 2007 - Publication
K. H. Chong, L. McMurchie and C. Sechen, A 64b Adder Using Self-calibrating Differential Out-put Prediction Logic, Proc. Int. Solid-State Circuits Conference (ISSCC), February 2006, San Fran-cisco, CA. 2006 - Publication
J. Zhang, M. Vujkovic, D. Wadkins, and C. Sechen, Post-Layout Energy-Delay Analysis of Parallel Multipliers, Proc. Int. Symp. on Circuits and Systems (ISCAS), May 2006, Greece. 2006 - Publication
Sheng Sun, Larry McMurchie and Carl Sechen, WTAWaveform-Based Timing Analysis for Deep Submicron Static CMOS and Dynamic Circuits, submitted December 2006 to: IEEE Trans. on CAD. 2006 - Publication
Appointments
Professor
The University of Texas at Dallas [2005–Present]
The University of Texas at Dallas [2005–Present]
Professor
University of Washington [1999–2005]
University of Washington [1999–2005]
Associate Professor
University of Washington [1992–1999]
University of Washington [1992–1999]
Associate Professor
Yale University [1990–1992]
Yale University [1990–1992]
Assistant Professor
Yale University [1986–1990]
Yale University [1986–1990]
Additional Information
Honors and Awards
- Fellow, Institute of Electrical and Electronics Engineers, 2002
- Outstanding Research Advisor Award, Department of Electrical Engineering, University of Washington, 2002
- Best Project Award, NSF Center for the Design of Digital and Analog ICs (CDADIC), 2002
- SRC Inventors Recognition Award, Semiconductor Research Corporation, 2001
- SRC Technical Excellence Award, Semiconductor Research Corporation, 1994
- SRC Inventor's Recognition Award, Semiconductor Research Corporation, 1988